Information processing apparatus with central processing unit and main memory having power saving mode, and power saving controlling method

ABSTRACT

A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an information processingapparatus, a power saving controlling method and a storage medium, andmore particularly to an information processing apparatus with a centralprocessing unit and a main memory having a power saving mode, a powersaving controlling method and a storage medium.

[0003] 2. Description of the Related Art

[0004] Power saving type CPU's have been widely used in informationprocessing apparatus having a power saving mode and a normal operationmode wherein the power saving mode is activated when a power saving modetransfer command (WAITI command) is executed and the operation mode isreturned to the normal operation mode when a hardware interruption isinput. In order to reduce a power consumption of the whole apparatus, apower saving mode is used for each of the constituent element of thesystem, and the power saving mode is activated for each constituentelement not used during the operation of the apparatus.

[0005] A main memory for storing programs and data to be used by a CPUis a constituent element which consumes a large power. Various powersaving modes for the main memory have been proposed. For example, theoperation mode of a main memory using a synchronous DRAM (SDRAM) can beswitched to a power saving mode by issuing a self refresh entry command(SELF command) to SDRAM.

[0006] Switching to such power saving mode is generally performed by thesettings of CPU. In order to make the whole apparatus transfers to thepower saving mode, first the main memory is required to transfer to thepower saving mode by setting with CPU and then CPU itself is required totransfer to the power saving mode. However, in order for CPU itself totransfer to the power saving mode, it is necessary to execute a WAITIcommand. This WAITI command is generally stored in the main memory sothat the main memory is required to be in the normal operation mode whenthe WAITI command is fetched.

[0007] When the operation mode is to be returned to the normal operationmode from the power saving mode by a hardware interruption, it isnecessary for CPU first to make settings so that the main memory canrecover the normal operation mode. However, immediately after CPUreturns to the normal operation mode, CPU fetches a command for aninterruption handler from the main memory. It is necessary that the mainmemory is in the normal operation mode at this time.

[0008] In order to satisfy the above-described requirements, inconventional arts, the main memory is divided into a static memoryhaving a small capacity and a low consumption power such as a ROM and anSRAM, and an SDRAM having a large capacity. A routine for executing theWAITI command and an interruption handler are made always resident inthe small capacity memory or they are transferred to the small capacitymemory immediately before the transfer to the power saving mode.

[0009] In the information processing apparatus, it is generallynecessary for CPU to fetch a command at a reset vector addressimmediately after the power is turned on. From this reason, theapparatus is provided with an inexpensive ROM (boot ROM) as a portion ofthe main memory. In a partial field of the boot ROM, the executionroutine for the WAITI command and the interruption handler are fixedlywritten beforehand to configure the apparatus without providing adedicated memory to the transfer to the power saving mode.Alternatively, if a CPU has a command cache, the operation mode istransferred to the power saving mode after the execution routine for theWAITI command and the interruption handler are locked down in thecommand cache. Namely, instead of using a dedicated SRAM, the commandcache is used for the same purpose.

[0010] The above-conventional arts are, however, associated with thefollowing problems. An inexpensive ROM has a longer access time than aRAM. Therefore, a command sequence in ROM is processed slower than acommand sequence in RAM. If the interruption handler is fixedly writtenin ROM, not only a process regarding the transfer from the power savingmode but also a process regarding a usual interruption process becomesslow. This problem is critical for information processing apparatus,particularly those performing a real time process.

[0011] An approach to providing a dedicated SRAM results in a rise ofthe apparatus cost because of expensive SRAM.

[0012] An approach to utilizing a command cache results in a largeprocess overhead and a low process speed, because each time theoperation mode transfers to the power saving mode, a necessary routineor handler is locked down in the cache by using a specific cacheoperation command. Further, software for handling the cache is likely tobecome complicated and debugging is difficult. Locking down in the cachemeans a substantial reduction of the field for storing other commands,which results in a lower hit rate of the cache and a lower performance.

SUMMARY OF THE INVENTION

[0013] The present invention has been made in consideration of theabove-described problems. It is an object of the present invention toprovide a power saving type information processing apparatus which isnot expensive and can provide a high interruption performance withoutusing an expensive and dedicated memory and a complicated softwareprocess, a power saving controlling method and a storage medium storinga program for realizing such method.

[0014] In order to achieve the above object, the invention provides aninformation processing apparatus comprising: central processing meanscapable of transferring from a normal operation mode to a power savingmode and returning to the power saving mode to the normal operationmode; main memory means capable of transferring from the normaloperation mode to the power saving mode and returning to the powersaving mode to the normal operation mode; and setting means for settingtransfer information of the main memory means from the normal operationmode to the power saving mode, wherein after the transfer information isset by the setting means, the central processing means executes a powersaving mode transfer command.

[0015] The invention also provides an information processing apparatuscomprising: central processing means having a normal operation mode anda power saving mode; main memory means having the normal operation modeand the power saving mode; storage means for storing transferinformation of the main memory means from the normal operation mode tothe power saving mode; detecting means for detecting a power saving modetransfer command sent to the central processing means; and transfercontrol means for making the main memory means transfer to the powersaving mode from the normal operation mode in accordance with thetransfer information stored in the storage means and a detection by thedetecting means.

[0016] The invention also provides a power saving controlling method foran information processing apparatus having a central processing unitcapable of transferring from a normal operation mode to a power savingmode and returning to the power saving mode to the normal operation modeand a main memory capable of transferring from the normal operation modeto the power saving mode and returning to the power saving mode to thenormal operation mode, the method comprising: a setting step of settingtransfer information of the main memory from the normal operation modeto the power saving mode; and an executing step of the centralprocessing unit executing a power saving mode transfer command after thetransfer information is set by the setting step.

[0017] The invention also provides a power saving controlling method foran information processing apparatus having a central processing unithaving a normal operation mode and a power saving mode and a main memoryhaving the normal operation mode and the power saving mode, the methodcomprising: a storing step of storing transfer information of the mainmemory from the normal operation mode to the power saving mode; adetecting step of detecting a power saving mode transfer command sent tothe central processing unit; and a transfer control step of making themain memory transfer to the power saving mode from the normal operationmode in accordance with the transfer information stored by the storingstep and a detection by the detecting step.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a block diagram showing the electronic structure of aninformation processing apparatus according to a first embodiment of theinvention.

[0019]FIG. 2 is a block diagram showing the internal structure of anSDRAM controller of the information processing apparatus of the firstembodiment.

[0020]FIG. 3 is a block diagram showing the electronic structure of aninformation processing apparatus according to a second embodiment of theinvention.

[0021]FIG. 4 is a block diagram showing the internal structure of anSDRAM controller of the information processing apparatus of the secondembodiment.

[0022]FIG. 5 is a block diagram showing the electronic structure of aninformation processing apparatus according to a third embodiment of theinvention.

[0023]FIG. 6 is a block diagram showing the internal structure of anSDRAM controller of the information processing apparatus of the thirdembodiment.

[0024]FIG. 7 is a diagram showing an example of the contents of astorage medium storing a program and related data for executing a powersaving mode transfer control method according to the invention.

[0025]FIG. 8 is a diagram conceptually illustrating how a storage mediumsupplies an apparatus with a program and related data for executing apower saving mode transfer control method according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Embodiments of the invention will be described in detail withreference to the accompanying drawings.

First Embodiment

[0027]FIG. 1 is a block diagram showing the electronic structure of aninformation processing apparatus according to the first embodiment ofthe invention. The information processing apparatus according to thefirst embodiment of the invention has a Central Processing Unit (CPU) 1,a ROM 2, an SDRAM (main memory) 3, a ROM controller 4, an SDRAMcontroller 5, an interruption controller 6, a WAITI command fetchdetecting circuit 7, and a system bus 8.

[0028] This structure will be detailed. CPU 1 is a power saving typecentral processing unit which executes a power saving mode transfercommand (WAITI command) to transfer to the power saving mode and returnsto the normal operation mode upon reception of a hardware interruption.Commands to be executed by CPU 1 are stored in ROM 2 and SDRAM 3. SDRAM3 also stores data necessary for the command execution by CPU 1. Acommand fetch/transfer of CPU 1 is generated as a transaction on thesystem bus 8. Upon detection of this transaction, the ROM controller 4or SDRAM controller 5 converts it into a memory access/transfer and anaccessed command in ROM 2 or SDRAM 3 is sent to the system bus 8.Similarly, data transfer by CPU 1 is also performed by the SDRAMcontroller 5 via the system bus 8.

[0029] Upon reception of an external trigger such as a switch depressionof the information processing apparatus, the interruption controller 6asserts a hardware interruption signal relative to CPU 1 and WAITIcommand fetch detecting circuit 7. The WAITI command fetch detectingcircuit 7 monitors a command fetch/transfer on the system bus 8. Whenthe WAITI command fetch detecting circuit 7 detects that the transfer onthe system bus is the command fetch transfer and data is the WAITIcommand, the circuit 7 asserts a WAITI command detecting signal relativeto the SDRAM controller 5. When a hardware interruption signal isasserted, the WAITI command detecting signal is negated.

[0030]FIG. 2 is a block diagram illustrating settings of the powersaving mode by the SDRAM controller 5 of the information processingapparatus of the first embodiment shown in FIG. 1. The SDRAM controller5 of the information processing apparatus of the first embodiment has anSDRAM setting register (setting means) 51, an AND gate 52 and an SDRAMcontrol sequencer 53.

[0031] The structure of the SDRAM controller 5 will be detailed. TheSDRAM setting register 51 is, for example, a 16-bit register connectedto 16-bit data lines of the system bus 8. This SDRAM setting register 51is memory-mapped as viewed from CPU 1, and for example, assigned with anaddress of 0×FF100000. A decode circuit (not shown) of the SDRAMcontroller 5 decodes the address lines of the system bus 8, and if theaddress of the transaction output from CPU 1 is the address 0×FF100000and the transaction is a write transaction, data on the data lines ofthe system bus 8 is latched to the SDRAM setting register 51.

[0032] The lowest bit (Bit 0) of the SDRAM setting register 51 is outputas a SELF allowance signal to one input terminal of the two-input ANDgate 52. To the other input terminal of the AND gate 52, a WAITI commanddetecting signal is input which indicates that CPU 1 fetched the WAITIcommand. An output of the AND gate 52 is supplied as an SELF requirementsignal to the SDRAM control sequencer 53.

[0033] When the SELF requirement signal is asserted as “1”, the SDRAMcontrol sequencer 53 issues a SELF command to SDRAM 3 immediately afterthe presently executing memory transfer is completed. This is realizedby driving a CS signal, a RAS signal, a CAS signal and a CKE signal allto “0” and a WE signal to “1”. Upon reception of the SELF command, SDRAM3 transfers to the power saving mode.

[0034] Next, the operation of the information processing apparatus ofthe first embodiment constructed as above will be described in detailwith reference to FIGS. 1 and 2. The control operation to be describedin the following is executed by CPU 1 in accordance with the programstored in ROM 2 of the information processing apparatus.

[0035] First, a procedure of transferring both CPU 1 and SDRAM 3 to thepower saving mode to be executed by CPU 1 will be described. CPU 1issues a write and transfer to the SDRAM setting register 51 of theSDRAM controller 5 and drives the data line Bit 0 of the system bus 8 to“1” so that the SELF allowance signal is set to “1”. At this time, theSDRAM controller 5 does not issue the SELF command immediately. It istherefore possible for CPU 1 to fetch the WAITI command from SDRAM 3,the WAITI command being a command to be executed last in the normaloperation mode.

[0036] When CPU 1 issues a command fetch transfer for fetching the WAITIcommand to the system bus 8, the WAITI command fetch detecting circuit 7asserts the WAITI command detecting signal as “1”. As a result, the SELFrequirement signal becomes “1” so that the SDRAM control sequencer 53 ofthe SDRAM controller 5 issues the SELF command to SDRAM 3 and SDRAM 3enters the power saving mode.

[0037] Next, a procedure of returning to the normal operation mode fromthe power saving mode will be described. When an external trigger isinput in response to the depression of a switch or the like of theinformation processing apparatus, the interruption controller 6 assertsa hardware interruption relative to CPU 1 and the WAITI command fetchdetecting circuit 7. Upon reception of the interruption, CPU 1 returnsto the normal operation mode and the WAITI command fetch detectingcircuit 7 negates the WAITI command detecting signal to “0”.

[0038] The SELF requirement signal of the SDRAM controller 5 istherefore negated so that the SDRAM control sequencer 53 of the SDRAMcontroller 5 immediately issues a SELF EXIT command to SDRAM 3. This isrealized by driving only the CS signal to “0” and all other signals (RASsignal, CAS signal, WE signal and CKE signal) to “1”. With the aboveoperations, SDRAM 3 returns to the normal operation mode.

[0039] CPU 1 returned to the normal operation mode outputs aninterruption vector address and a command fetch cycle to the system bus8 in order to immediately fetch the interruption handler command. SinceSDRAM 3 is already in the normal operation mode, the SDRAM controller 5immediately reads the requested command from SDRAM 3 and outputs it tothe system bus 8.

[0040] As described above, according to the first embodiment of theinvention, in the information processing apparatus having CPU 1 capableof transferring to the power saving mode from the normal operation modeand returning to the normal operation mode from the power saving modeand SDRAM 3 capable of transferring to the power saving mode from thenormal operation mode and returning to the normal operation mode fromthe power saving mode, the SDRAM setting register 51 of the SDRAMcontroller 5 outputs the SELF allowance signal for allowing SDRAM 3 totransfer to the power saving mode from the normal operation mode, andthereafter the WAITI command fetch detecting circuit 7 outputs the WAITIcommand detecting signal. In this case, SDRAM 3 is transferred to thepower saving mode. When CPU 1 detects the external interruption forreturning to the normal operation mode from the power saving mode whileSRAM 3 is in the power saving mode, the operation mode of SDRAM 3 isreturned to the normal operation mode irrespective of settings of theSDRAM setting register 51. Accordingly, the following advantageouseffects can be obtained.

[0041] SDRAM 3 can operate normally when the WAITI command is fetched totransfer to the power saving mode, without using an expensive dedicatedmemory and a complicated software process, because SDRAM 3 istransferred to the power saving mode after CPU 1 reliably transfers tothe power saving mode. Further, SDRAM 3 can fetch the interruptionhandler command to return to the normal operation mode. Since theinterruption handler can be made always resident in a high speed RAMwithout wastefully using the cache field, a high performance can bemaintained and a complicated software process is not necessary. It istherefore easy to configure a power saving type information processingapparatus which is not expensive and has a high interruptionperformance.

Second Embodiment

[0042]FIG. 3 is a block diagram showing the electronic structure of aninformation processing apparatus according to the second embodiment ofthe invention. The information processing apparatus according to thesecond embodiment of the invention has a Central Processing Unit (CPU)61, a ROM 62, an SDRAM (main memory) 63, a ROM controller 64, an SDRAMcontroller 65, an interruption controller 66, and a system bus 67.

[0043] This structure will be detailed. CPU 61 is a power saving typecentral processing unit which executes a power saving mode transfercommand (WAITI command) to transfer to the power saving mode and returnsto the normal operation mode upon reception of a hardware interruption.Commands to be executed by CPU 61 are stored in ROM 62 and SDRAM 63.SDRAM 63 also stores data necessary for the command execution by CPU 61.

[0044] A command fetch/transfer of CPU 61 is generated as a transactionon the system bus 67. Upon detection of this transaction, the ROMcontroller 64 or SDRAM controller 65 converts it into a memoryaccess/transfer and an accessed command in ROM 62 or SDRAM 63 is sent tothe system bus 67. Similarly, data transfer by CPU 61 is also performedby the SDRAM controller 65 via the system bus 67. Upon reception of anexternal trigger such as a switch depression of the informationprocessing apparatus, the interruption controller 66 asserts a hardwareinterruption signal relative to CPU 61 and SDRAM controller 65.

[0045]FIG. 4 is a block diagram illustrating settings of the powersaving mode by the SDRAM controller 65 of the information processingapparatus of the second embodiment shown in FIG. 3. The SDRAM controller65 of the information processing apparatus of the second embodiment hasan SDRAM counter 71 and an SDRAM control sequencer 72, the SDRAM counter71 including an SDRAM control register 711, an SDRAM counter register(time setting means) 712 and an SDRAM counter work register 713.

[0046] The structure of the SDRAM controller 65 will be detailed. TheSDRAM control register 711, SDRAM counter register 712 and SDRAM counterwork register 713 are, for example, a 16-bit register. Of theseregisters, the SDRAM control register 711 and SDRAM counter register 712are connected to 16-bit data lines of the system bus 67. The SDRAMcontrol register 711 and SDRAM counter register 712 are memory-mapped asviewed from CPU 61. For example, the SDRAM control register 711 isassigned with an address of 0×FF100000, whereas the SDRAM counterregister 712 is assigned with an address of 0×FF100004.

[0047] If a transaction output from CPU 61 is a write transaction, adecode circuit (not shown) of the SDRAM controller 65 decodes theaddress lines of the system bus 67 and data is latched to the SDRAMcontrol register 711 if the address is 0×FF100000 and to the SDRAMcounter register 712 if the address is 0×FF100004.

[0048] When “1” is written to the lowest bit (Bit 0) of the SDRAMcontrol register 711, the SDRAM counter 71 transfers the contents of theSDRAM counter register 712 to the SDRAM counter work resister 713. Inresponse to a clock signal (now shown), the contents of the SDRAMcounter work register 713 are counted down until all the bits become“0”. Only when all the bits of the SDRAM counter work register 713become “0” and the lowest bit (Bit 0) of the SDRAM control register 711is “1”, a SELF requirement signal connected to the SDRAM controlsequencer 72 is set to “1”. When the hardware interruption signal isasserted, the lowest bit (Bit 0) of the SDRAM control register 711 isreset to “0”.

[0049] When the SELF requirement signal is asserted as “1”, the SDRAMcontrol sequencer 72 issues a SELF command to SDRAM 63 immediately afterthe presently executing memory transfer is completed. This is realizedby driving a CS signal, a RAS signal, a CAS signal and a CKE signal allto “0” and a WE signal to “1”. Upon reception of the SELF command, SDRAM63 transfers to the power saving mode.

[0050] When the SELF requirement signal is negated to “0”, the SDRAMcontrol sequencer 72 immediately issues a SELF EXIT command to SDRAM 63.This is realized by driving only the CS signal to “0” and all the othersignals (RAS signal, CAS signal, WE signal and CKE signal) to “1”. SDRAM63 therefore returns to the normal operation mode.

[0051] Next, the operation of the information processing apparatus ofthe second embodiment constructed as above will be described in detailwith reference to FIGS. 3 and 4. The control operation to be describedin the following is executed by CPU 61 in accordance with the programstored in ROM 62 of the information processing apparatus.

[0052] First, a procedure of transferring both CPU 61 and SDRAM 63 tothe power saving mode to be executed by CPU 61 will be described. CPU 61issues a write transfer to the address assigned to the SDRAM counterregister 712 of the SDRAM controller 65 to set a time taken from thecount-down start to the transfer to the power saving mode to the SDRAMcounter register 712. Next, CPU 61 issues a write transfer to theaddress assigned to the SDRAM control register 711 to set “1” to thelowest bit (Bit 0) of the SDRAM control register 711. With the aboveoperations, the SDRAM counter 71 transfers the contents of the SDRAMcounter register 712 to the SDRAM work register 713 to start thecount-down thereof.

[0053] Since the SELF requirement signal is not asserted to “1” untilall the bits of the SDRAM counter work register 713 become “0”, SDRAM 63is in the normal operation mode at this time. During this period, CPU 61executes the WAITI command for transferring CPU itself to the powersaving mode. Thereafter, when all the bits of the SDRAM counter workregister 713 become “0”, the SELF requirement signal is asserted to “1”and the SDRAM control sequencer 72 issues the SELF command to SDRAM 63to make SDRAM 63 enter the power saving mode.

[0054] Next, a procedure of returning to the normal operation mode fromthe power saving mode will be described. When an external trigger isinput in response to the depression of a switch or the like of theinformation processing apparatus, the interruption controller 66 assertsa hardware interruption. Therefore, CPU 61 immediately returns to thenormal operation mode, and the SDRAM counter 71 resets the lowest bit(Bit 0) of the SDRAM control register 711 to “0” and negates the SELFrequirement signal to “0”. The SDRAM control sequencer 72 immediatelyissues a SELF EXIT command to SDRAM 63 to make it enter the normaloperation mode.

[0055] CPU 61 returned to the normal operation mode outputs aninterruption vector address and a command fetch cycle to the system bus67 in order to immediately fetch the interruption handler command. SinceSDRAM 63 is already in the normal operation mode, the SDRAM controller65 immediately reads the requested command from SDRAM 63 and outputs itto the system bus 67.

[0056] As described above, according to the second embodiment of theinvention, in the information processing apparatus having CPU 61 capableof transferring to the power saving mode from the normal operation modeand returning to the normal operation mode from the power saving modeand SDRAM 63 capable of transferring to the power saving mode from thenormal operation mode and returning to the normal operation mode fromthe power saving mode, CPU 61 sets the time taken to transfer to thepower saving mode from the normal operation mode to SDRAM 63, andinstructs SDRAM 63 to transfer to the power saving mode after a lapse ofthe set time. When SDRAM 63 receives this instruction, SDRAM 63 iscontrolled to transfer to the power saving mode after a lapse of the settime. Accordingly, the following advantageous effects can be obtained.

[0057] SDRAM 63 can operate normally when the WAITI command is fetchedto transfer to the power saving mode, without using an expensivededicated memory. Further, SDRAM 63 can fetch the interruption handlercommand to return to the normal operation mode. After the booting, theinterruption handler and the like in ROM 62 are transferred to a highspeed SDRAM 63. It is therefore possible to execute the interruptionhandler at high speed without wastefully using a cache field and thelike and without using a complicated software process. It is thereforeeasy to configure a power saving type information processing apparatuswhich is not expensive and has a high interruption performance.

Third Embodiment

[0058]FIG. 5 is a block diagram showing the electronic structure of aninformation processing apparatus according to the third embodiment ofthe invention. The information processing apparatus according to thethird embodiment of the invention has a Central Processing Unit (CPU)81, a ROM 82, an SDRAM (main memory) 83, a ROM controller 84, an SDRAMcontroller 85, an interruption controller 86, and a system bus 87.

[0059] This structure will be detailed. CPU 81 is a power saving typecentral processing unit which executes a power saving mode transfercommand (WAITI command) to transfer to the power saving mode and returnsto the normal operation mode upon reception of a hardware interruption.Commands to be executed by CPU 81 are stored in ROM 82 and SDRAM 83.SDRAM 83 also stores data necessary for the command execution by CPU 81.

[0060] A command fetch/transfer of CPU 81 is generated as a transactionon the system bus 87. Upon detection of this transaction, the ROMcontroller 84 or SDRAM controller 85 converts it into a memoryaccess/transfer and an accessed command in ROM 82 or SDRAM 83 is sent tothe system bus 87. Similarly, data transfer by CPU 81 is also performedby the SDRAM controller 85 via the system bus 87. Upon reception of anexternal trigger such as a switch depression of the informationprocessing apparatus, the interruption controller 86 asserts a hardwareinterruption signal relative to CPU 81.

[0061]FIG. 6 is a block diagram illustrating settings of the powersaving mode by the SDRAM controller 85 of the information processingapparatus of the third embodiment shown in FIG. 5. The SDRAM controller85 of the information processing apparatus of the third embodiment hasan SDRAM setting register 91, an AND gate 92 and an SDRAM controlsequencer 93.

[0062] The structure of the SDRAM controller 85 will be detailed. TheSDRAM setting register 91 is, for example, a 16-bit register connectedto 16-bit data lines of the system bus 87. This SDRAM setting register91 is memory-mapped as viewed from CPU 81, and for example, assignedwith an address of 0×FF100000. A decode circuit (not shown) of the SDRAMcontroller 85 decodes the address lines of the system bus 87, and if theaddress of the transaction output from CPU 81 is the address 0×FF100000and the transaction is a write transaction, data on the data lines ofthe system bus 87 is latched to the SDRAM setting register 91.

[0063] The lowest bit (Bit 0) of the SDRAM setting register 91 is outputas a SELF allowance signal to one input terminal of the two-input ANDgate 92. To the other input terminal of the AND gate 92, a WAITI signalis input which indicates that CPU 81 transferred to the power savingmode. An output of the AND gate 92 is supplied as an SELF requirementsignal to the SDRAM control sequencer 93.

[0064] When the SELF requirement signal is asserted as “1”, the SDRAMcontrol sequencer 93 issues a SELF command to SDRAM 8 immediately afterthe presently executing memory transfer is completed. This is realizedby driving a CS signal, a RAS signal, a CAS signal and a CKE signal allto “0” and a WE signal to “2”. Upon reception of the SELF command, SDRAM83 transfers to the power saving mode.

[0065] Next, the operation of the information processing apparatus ofthe third embodiment constructed as above will be described in detailwith reference to FIGS. 5 and 6. The control operation to be describedin the following is executed by CPU 81 in accordance with the programstored in ROM 82 of the information processing apparatus.

[0066] First, a procedure of transferring both CPU 81 and SDRAM 83 tothe power saving mode to be executed by CPU 81 will be described. CPU 81issues a write transfer to the SDRAM setting register 91 of the SDRAMcontroller 85 and drives the data line Bit 0 of the system bus 87 to “1”so that the SELF allowance signal is set to “1”. At this time, the SDRAMcontroller 85 does not issue the SELF command immediately. It istherefore possible for CPU 81 to fetch the WAITI command from SDRAM 83,the WAITI command being a command to be executed last in the normaloperation mode.

[0067] When CPU 81 executes the WAITI command and completes the transferto the power saving mode, the WAITI signal which is a power saving modenotifying signal is asserted to “1”. As a result, the SELF requirementsignal becomes “1” so that the SDRAM control sequencer 93 issues theSELF command to SDRAM 83 and SDRAM 83 enters the power saving mode.

[0068] Next, a procedure of returning to the normal operation mode fromthe power saving mode will be described. When an external trigger isinput in response to the depression of a switch or the like of theinformation processing apparatus, the interruption controller 86 assertsa hardware interruption relative to CPU 81. Upon reception of theinterruption, CPU 81 immediately returns to the normal operation modeand the power saving mode notifying signal (WAITI signal) is negated to“0”.

[0069] The SELF requirement signal of the SDRAM controller 85 istherefore negated so that the SDRAM control sequencer 93 of the SDRAMcontroller 85 immediately issues a SELF EXIT command to SDRAM 83. Thisis realized by driving only the CS signal to “0”and all other signals(RAS signal, CAS signal, WE signal and CKE signal) to “2”. With theabove operations, SDRAM 83 returns to the normal operation mode.

[0070] CPU 81 returned to the normal operation mode outputs aninterruption vector address and a command fetch cycle to the system bus87 in order to immediately fetch the interruption handler command. SinceSDRAM 83 is already in the normal operation mode, the SDRAM controller85 can immediately read the requested command from SDRAM 83 and outputit to the system bus 87.

[0071] As described above, according to the third embodiment of theinvention, in the information processing apparatus having CPU 81 capableof transferring to the power saving mode from the normal operation modeand returning to the normal operation mode from the power saving modeand SDRAM 83 capable of transferring to the power saving mode from thenormal operation mode and returning to the normal operation mode fromthe power saving mode, when the transfer of CPU 81 to the power savingmode is notified, CPU 81 makes settings so that SDRAM 83 is allowed tochange the operation mode from the normal operation mode to the powersaving mode, and the notification of the transfer to the power savingmode is received from a notifying means after SDRAM 83 is allowed totransfer to the power saving mode, SDRAM 83 is controlled to transfer tothe power saving mode. Accordingly, the following advantageous effectscan be obtained.

[0072] SDRAM 83 can operate normally when the WAITI command is fetchedto transfer to the power saving mode, without using an expensivededicated memory. Further, SDRAM 83 can fetch the interruption handlercommand to return to the normal operation mode. Since the interruptionhandler can be made always resident in a high speed RAM withoutwastefully using the cache field, a high performance can be maintainedand a complicated software process is not necessary. It is thereforeeasy to configure a power saving type information processing apparatuswhich is not expensive and has a high interruption performance.

Other Embodiments

[0073] In the first to third embodiments of the invention, the type ofthe information processing apparatus is not specified. The invention isalso applicable to various types of information processing apparatussuch as a desk top personal computer, a note type personal computer, aportable information terminal, and a work station.

[0074] In the first to third embodiments of the invention, a singleinformation processing apparatus is used. The invention is alsoapplicable to a system having an information processing apparatus, animage forming apparatus such as a copier and a printer, and an imagereading apparatus such as a scanner, respectively interconnected via acommunication medium such as a network.

[0075]FIG. 8 is a diagram conceptually illustrating how a storage mediumsupplies an apparatus with a program and related data for executing apower saving mode transfer control method according to the invention.The program and related data for executing the power saving modetransfer control method of the invention are supplied by inserting astorage medium 111 such as a FLOPPY TM disk and a CD-ROM into a storagemedium insertion port 113 of an apparatus 112 such as a computer.Thereafter, the program and related data in the storage medium 111 areonce installed in a hard disk and then loaded in a RAM, or directlyloaded in a RAM without installing them in a hard disk. In this manner,the program and related data can be used.

[0076] In this case, when the program for executing the power savingmode transfer control method of this invention is to be executed by theinformation processing apparatus of the first to third embodiments, theprogram and related data are supplied to the information processingapparatus in the manner described with reference to FIG. 8, or loadedbeforehand in the information processing apparatus.

[0077]FIG. 7 is a diagram showing an example of the contents of astorage medium storing a program and related data for executing a powersaving mode transfer control method of the invention. For example, thestorage medium stores therein volume information 101, directoryinformation 102, a program executing file 103, a program related datafile 104 and the like. The program for executing the power saving modetransfer control method of the invention is constituted of program codesrealizing the control procedure described with the first to thirdembodiments.

[0078] The invention is applicable to a system having a plurality ofapparatuses or to a single apparatus. Obviously, a storage mediumstoring software program codes realizing the function of each embodimentdescribed above may be supplied to a system or apparatus to make acomputer (CPU or MPU) of the system or apparatus read the program codesstored in the storage medium.

[0079] In this case, the software program codes themselves read from thestorage medium realize the embodiment function. Therefore, the storagemedium storing the program codes constitutes the invention. The storagemedium for storing such program codes may be a FLOPPY TM disk, a harddisk, an optical disk, a magneto optical disk, a CD-ROM, a CD-R, amagnetic tape, a nonvolatile memory card, a ROM or the like. The programcodes may be downloaded via a network.

[0080] It is obvious that not only the computer reads and executes theprogram codes to realize the embodiment function but also the programcodes are executed in cooperation with an OS running on the computerwhich OS performs a portion or the whole of actual processes to realizethe embodiment function.

[0081] It is obvious that the scope of the invention also contains thecase wherein the functions of each embodiment can be realized by writingthe program codes read from the storage medium into a memory of afunction expansion board inserted into a computer or of a functionexpansion unit connected to the computer, and thereafter by executing aportion or the whole of actual processes by a CPU of the functionexpansion board or function expansion unit.

What is claimed is:
 1. An information processing apparatus comprising: acentral processing means capable of transferring from a normal operationmode to a power saving mode and returning to the power saving mode tothe normal operation mode; a main memory means capable of transferringfrom a normal operation mode to a power saving mode and returning to thepower saving mode to the normal operation mode; and a setting means forsetting transfer information of said main memory means from a normaloperation mode to a power saving mode, wherein said central processingmeans executes a power saving mode transfer command after the transferinformation is set by said setting means.
 2. An information processingapparatus according to claim 1, further comprising: a detecting meansfor detecting that said central processing means fetched the powersaving mode transfer command; and a transfer control means fortransferring said main memory means to a power saving mode if saiddetecting means detects that the power saving mode transfer command isfetched after said setting means sets the transfer information.
 3. Aninformation processing apparatus according to claim 1, furthercomprising: a returning means for making said main memory means returnto a normal operation mode irrespective of settings by said settingmeans, if said central processing means detects an external interruptionfor returning to a normal operation mode from a power saving mode whilesaid main memory means is in the power saving mode.
 4. An informationprocessing apparatus according to claim 1, wherein the transferinformation is a time taken to transfer to a power saving mode from anormal operation mode, and the information processing apparatus furthercomprises a transfer control means for controlling to transfer said mainmemory means to a power saving mode after a lapse of the set time of thetransfer information.
 5. An information processing apparatus accordingto claim 4, further comprising: an instructing means for instructing atransfer to the power saving mode, wherein said transfer control meanscontrols to transfer said main memory means to a power saving mode afterthe lapse of the set time of the transfer information, in accordancewith an instruction of said instructing means.
 6. An informationprocessing apparatus according to claim 1, further comprising: anotifying means for notifying that said central processing means wastransferred to a power saving mode; and a transfer control means fortransferring said main memory means to a power saving mode after thetransfer information is set by said setting means, in response to anotice of said notifying means.
 7. An information processing apparatuscomprising: a central processing means having a normal operation modeand a power saving mode; a main memory means having a normal operationmode and a power saving mode; a storage means for storing transferinformation of said main memory means from a normal operation mode to apower saving mode; a detecting means for detecting a power saving modetransfer command sent to said central processing means; and a transfercontrol means for making said main memory means transfer to a powersaving mode from a normal operation mode in accordance with the transferinformation stored in said storage means and a detection by saiddetecting means.
 8. An information processing apparatus according toclaim 7, wherein said transfer control means supplies said main memorymeans with a predetermined signal to make said main memory means totransfer to a power saving mode from a normal operation mode.
 9. Aninformation processing apparatus according to claim 7, furthercomprising: a returning means for making said main memory means returnto a normal operation mode, if said central processing means detects anexternal interruption for returning to a normal operation mode from apower saving mode while said main memory means is in the power savingmode.
 10. A power saving controlling method for an informationprocessing apparatus having a central processing unit capable oftransferring from a normal operation mode to a power saving mode andreturning to the power saving mode to the normal operation mode and amain memory capable of transferring from a normal operation mode to apower saving mode and returning to the power saving mode to the normaloperation mode, the method comprising: a setting step of settingtransfer information of the main memory from a normal operation mode toa power saving mode; and an executing step of the central processingunit executing a power saving mode transfer command after the transferinformation is set by said setting step.
 11. A power saving controllingmethod according to claim 10, further comprising: a detecting step ofdetecting that the central processing unit fetched the power saving modetransfer command; and a transfer control step of transferring the mainmemory to a power saving mode if said detecting step detects that thepower saving mode transfer command is fetched after said setting stepsets the transfer information.
 12. A power saving controlling methodaccording to claim 10, further comprising: a returning step of formaking the main memory return to a normal operation mode irrespective ofsettings by said setting step, if the central processing unit detects anexternal interruption for returning to a normal operation mode from apower saving mode while the main memory is in the power saving mode. 13.A power saving controlling method according to claim 10, wherein thetransfer information is a time taken to transfer to a power saving modefrom a normal operation mode, and the information processing methodfurther comprises a transfer control step of controlling to transfer themain memory to a power saving mode after a lapse of the set time of thetransfer information.
 14. A power saving controlling method according toclaim 13, further comprising: an instructing step of instructing atransfer to the power saving mode, wherein said transfer control stepcontrols to transfer the main memory to a power saving mode after thelapse of the set time of the transfer information, in accordance with aninstruction of said instructing step.
 15. A power saving controllingmethod according to claim 10, further comprising: a notifying step ofnotifying that the central processing unit was transferred to a powersaving mode; and a transfer control step of transferring the main memoryto a power saving mode after the transfer information is set by saidsetting step, in response to a notice of said notifying step.
 16. Apower saving controlling method for an information processing apparatushaving a central processing unit having a normal operation mode and apower saving mode and a main memory having a normal operation mode and apower saving mode, the method comprising: a storing step of storingtransfer information of the main memory from a normal operation mode toa power saving mode; a detecting step of detecting a power saving modetransfer command sent to the central processing unit; and a transfercontrol step of making the main memory transfer to a power saving modefrom a normal operation mode in accordance with the transfer informationstored by said storing step and a detection by said detecting step. 17.A power saving controlling method according to claim 16, wherein saidtransfer control step supplies the main memory with a predeterminedsignal to make the main memory to transfer to the power saving mode fromthe normal operation mode.
 18. A power saving controlling methodaccording to claim 16, further comprising: a returning step of formaking the main memory return to a normal operation mode, if the centralprocessing unit detects an external interruption for returning to thenormal operation mode from the power saving mode while the main memoryis in the power saving mode.
 19. A computer readable storage mediumstoring a program for controlling an information an informationprocessing apparatus having a central processing unit capable oftransferring from a normal operation mode to a power saving mode andreturning to the power saving mode to the normal operation mode and amain memory capable of transferring from a normal operation mode to apower saving mode and returning to the power saving mode to the normaloperation mode, the program comprising: a setting step of settingtransfer information of the main memory from a normal operation mode toa power saving mode; and an executing step of the central processingunit executing a power saving mode transfer command after the transferinformation is set by said setting step.
 20. A computer readable storagemedium according to claim 19, wherein the program further comprises: adetecting step of detecting that the central processing unit fetched thepower saving mode transfer command; and a transfer control step oftransferring the main memory to a power saving mode if said detectingstep detects that the power saving mode transfer command is fetchedafter said setting step sets the transfer information.
 21. A computerreadable storage medium according to claim 19, wherein the programfurther comprises: a returning step of for making the main memory returnto the normal operation mode irrespective of settings by said settingstep, if the central processing unit detects an external interruptionfor returning to the normal operation mode from the power saving modewhile the main memory is in the power saving mode.
 22. A computerreadable storage medium according to claim 19, wherein the transferinformation is a time taken to transfer to a power saving mode from anormal operation mode, and the program further comprises a transfercontrol step of controlling to transfer the main memory to a powersaving mode after a lapse of the set time of the transfer information.23. A computer readable storage medium according to claim 22, whereinthe program further comprises: an instructing step of instructing atransfer to the power saving mode, wherein said transfer control stepcontrols to transfer the main memory to a power saving mode after thelapse of the set time of the transfer information, in accordance with aninstruction of said instructing step.
 24. A computer readable storagemedium according to claim 19, wherein the program further comprises: anotifying step of notifying that the central processing unit wastransferred to a power saving mode; and a transfer control step oftransferring the main memory to a power saving mode after the transferinformation is set by said setting step, in response to a notice of saidnotifying step.
 25. A computer readable storage medium storing a programfor controlling an information processing apparatus having a centralprocessing unit having a normal operation mode and a power saving modeand a main memory having a normal operation mode and a power savingmode, the program comprising: a storing step of storing transferinformation of the main memory from a normal operation mode to a powersaving mode; a detecting step of detecting a power saving mode transfercommand sent to the central processing unit; and a transfer control stepof making the main memory transfer to a power saving mode from a normaloperation mode in accordance with the transfer information stored bysaid storing step and a detection by said detecting step.
 26. A computerreadable storage medium according to claim 25, wherein said transfercontrol step supplies the main memory with a predetermined signal tomake the main memory to transfer to a power saving mode from a normaloperation mode.
 27. A computer readable storage medium according toclaim 25, wherein the program further comprises: a returning step of formaking the main memory return to a normal operation mode, if the centralprocessing unit detects an external interruption for returning to thenormal operation mode from the power saving mode while the main memoryis in the power saving mode.